1. Field of the Invention
The present invention is directed to an input/output (I/O) buffer circuit and, in particular, to a low ground bounce output driver that in its preferred embodiment, utilizes novel bias generator circuitry to minimize both ground bounce and V.sub.cc bounce while providing nearly constant propagation delay independent of processing/voltage/temperature (PVT) variations.
2. Discussion of the Prior Art
High speed CMOS I/O buffers during large capacitive loads can generate very large transient ground currents when their outputs switch from high to low. These transient ground currents must flow through the parasitic ground line inductance which is inevitably present. (This parasitic inductance is primarily composed of package leadframe inductance, bondwire inductance and PC board trace inductance). Large transient ground currents flowing through this inductance can generate large transient voltage spikes on the on-chip ground lines, causing them to become very noisy. This well-known phenomenon, commonly known as "ground bounce", cart result in several harmful effects. For example, CMOS output drivers which are switching from high to low can adversely affect the logic zero output voltage produced by non-switching output buffers sharing the same ground line. This problem can become especially severe when, due to package pin limitations, many output drivers must share the same ground line. Ground bounce can also adversely affect mixed signal CMOS products containing on-chip analog circuitry.
FIG. 1 shows a conventional output driver circuit 10. When the input signal (data-in) to the output driver 10 is a logical high, predriver inverter 12 causes PMOS pull-up transistor 14 to be on and predriver inverter 16 causes NMOS pull-down transistor 18 to be off resulting in a logical high signal at the output pad 20. Conversely, when the input signal (data-in) is a logical low, PMOS transistor 14 is off and NMOS transistor 18 is on resulting in a logical low signal at the output pad 20.
FIG. 2 shows a CMOS circuit having eight I/O buffers connected to a shared on-chip ground line. The output drivers are of the type shown in FIG. 1, but only the NMOS pull-down transistor 18 of the FIG. 1 circuit is shown for each output driver. Of course, those skilled in the an will appreciate that any number of output drivers can be connected to the shared ground line.
Several prior an solutions to the ground bounce problem simply slow down the speed of the circuit. This solution is undesirable, however, because it results in decreased circuit performance.
U.S. Pat. No. 5,214,320 discloses a design technique for controlling the high-to-low transition time, and thus the ground bounce, of the output signal of a CMOS output driver. More specifically, the '320 patent discloses the use of an additional FET in the predriver inverter which drives the n-channel pull-down transistor. This FET is driven by a separate voltage reference signal which is above the threshold of the FET. Thus, while the additional FET is not fully on or fully off, it introduces additional resistance into the predriver, slowing down the rate of charge supplied to the gate of the n-channel pull-down transistor, in correspondence to the magnitude of the voltage reference signal. Reducing the charging rate supplied to the n-channel output device increases it's turn-on time, thereby increasing the switching time of the output signal. As a result, the magnitude of the ground bounce introduced by the output buffer is reduced, albeit at some cost in circuit performance.
The speed of the circuit disclosed in the '320 patent must be guaranteed under weak PVT conditions. When this is achieved, the same circuit must also perform to the same speed specifications under strong PVT conditions. Strong PVT conditions will cause the circuit to operate faster, however, resulting in unnecessary additional speed at the cost of additional ground bounce. Although the '320 patent discloses a reference voltage generator which provides some PVT compensation, this generator cannot be designed to produce the same circuit speed under weak PVT and strong PVT conditions.
It would therefore be highly desirable to have available a bias generator circuit which will slow down the output driver circuit under strong PVT conditions, but not under weak PVT conditions, resulting in a constant circuit operating speed which is independent PVT conditions. As discussed below, the present invention contains a bias generator circuit which reduces ground bounce and causes the speed of the circuit to be the same under both strong and weak PVT conditions.